| 1 | ShaderType = IL_SHADER_PIXEL |
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| 2 | TargetChip = c |
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| 3 | ; ------------- SC_SRCSHADER Dump ------------------ |
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| 4 | SC_SHADERSTATE: u32NumIntVSConst = 0 |
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| 5 | SC_SHADERSTATE: u32NumIntPSConst = 0 |
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| 6 | SC_SHADERSTATE: u32NumIntGSConst = 0 |
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| 7 | SC_SHADERSTATE: u32NumBoolVSConst = 0 |
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| 8 | SC_SHADERSTATE: u32NumBoolPSConst = 0 |
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| 9 | SC_SHADERSTATE: u32NumBoolGSConst = 0 |
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| 10 | SC_SHADERSTATE: u32NumFloatVSConst = 0 |
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| 11 | SC_SHADERSTATE: u32NumFloatPSConst = 0 |
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| 12 | SC_SHADERSTATE: u32NumFloatGSConst = 0 |
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| 13 | fConstantsAvailable = 4208439 |
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| 14 | iConstantsAvailable = 4208439 |
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| 15 | bConstantsAvailable = 4208439 |
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| 16 | u32SCOptions[0] = 0x01A00000 SCOption_IGNORE_SAMPLE_L_BUG SCOption_FLOAT_DO_NOT_DIST SCOption_FLOAT_DO_NOT_REASSOC |
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| 17 | u32SCOptions[1] = 0x00202000 SCOption_R600_ERROR_ON_DOUBLE_MEMEXP SCOption_SET_VPM_FOR_SCATTER |
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| 18 | u32SCOptions[2] = 0x00000040 SCOption_R800_UAV_NONUAV_SYNC_WORKAROUND_BUG216513_1 |
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| 19 | |
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| 20 | ; -------- Disassembly -------------------- |
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| 21 | 00 ALU: ADDR(32) CNT(68) |
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| 22 | 0 x: FLOOR*2 R4.x, R0.x |
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| 23 | y: FLOOR*2 R4.y, R0.y |
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| 24 | z: MOV R4.z, (0xC0000000, -2.0f).x |
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| 25 | t: MOV R11.x, 0.0f |
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| 26 | 1 x: MOV R10.x, 0.0f |
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| 27 | y: MOV R11.y, 0.0f |
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| 28 | z: MOV R11.z, 0.0f |
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| 29 | w: MOV R11.w, 0.0f |
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| 30 | t: MOV R10.y, 0.0f |
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| 31 | 2 x: MOV R9.x, 0.0f |
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| 32 | y: MOV R9.y, 0.0f |
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| 33 | z: MOV R10.z, 0.0f |
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| 34 | w: MOV R10.w, 0.0f |
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| 35 | t: MOV R9.z, 0.0f |
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| 36 | 3 x: MOV R23.x, 0.0f |
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| 37 | y: MOV R23.y, 0.0f |
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| 38 | z: MOV R23.z, 0.0f |
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| 39 | w: MOV R9.w, 0.0f |
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| 40 | t: MOV R23.w, 0.0f |
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| 41 | 4 x: MOV R8.x, 0.0f |
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| 42 | y: MOV R8.y, 0.0f |
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| 43 | z: MOV R8.z, 0.0f |
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| 44 | w: MOV R8.w, 0.0f |
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| 45 | t: MOV R22.x, 0.0f |
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| 46 | 5 x: MOV R21.x, 0.0f |
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| 47 | y: MOV R22.y, 0.0f |
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| 48 | z: MOV R22.z, 0.0f |
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| 49 | w: MOV R22.w, 0.0f |
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| 50 | t: MOV R21.y, 0.0f |
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| 51 | 6 x: MOV R20.x, 0.0f |
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| 52 | y: MOV R20.y, 0.0f |
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| 53 | z: MOV R21.z, 0.0f |
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| 54 | w: MOV R21.w, 0.0f |
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| 55 | t: MOV R20.z, 0.0f |
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| 56 | 7 x: MOV R15.x, 0.0f |
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| 57 | y: MOV R15.y, 0.0f |
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| 58 | z: MOV R15.z, 0.0f |
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| 59 | w: MOV R20.w, 0.0f |
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| 60 | t: MOV R15.w, 0.0f |
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| 61 | 8 x: MOV R14.x, 0.0f |
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| 62 | y: MOV R14.y, 0.0f |
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| 63 | z: MOV R14.z, 0.0f |
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| 64 | w: MOV R14.w, 0.0f |
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| 65 | t: MOV R13.x, 0.0f |
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| 66 | 9 x: MOV R12.x, 0.0f |
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| 67 | y: MOV R13.y, 0.0f |
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| 68 | z: MOV R13.z, 0.0f |
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| 69 | w: MOV R13.w, 0.0f |
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| 70 | t: MOV R12.y, 0.0f |
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| 71 | 10 x: MOV R19.x, 0.0f |
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| 72 | y: MOV R19.y, 0.0f |
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| 73 | z: MOV R12.z, 0.0f |
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| 74 | w: MOV R12.w, 0.0f |
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| 75 | t: MOV R19.z, 0.0f |
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| 76 | 11 x: MOV R18.x, 0.0f |
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| 77 | y: MOV R18.y, 0.0f |
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| 78 | z: MOV R18.z, 0.0f |
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| 79 | w: MOV R19.w, 0.0f |
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| 80 | t: MOV R18.w, 0.0f |
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| 81 | 12 x: MOV R17.x, 0.0f |
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| 82 | y: MOV R17.y, 0.0f |
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| 83 | z: MOV R17.z, 0.0f |
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| 84 | w: MOV R17.w, 0.0f |
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| 85 | t: MOV R16.x, 0.0f |
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| 86 | 13 y: MOV R16.y, 0.0f |
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| 87 | z: MOV R16.z, 0.0f |
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| 88 | w: MOV R16.w, 0.0f |
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| 89 | 01 LOOP_DX10 i0 FAIL_JUMP_ADDR(7) |
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| 90 | 02 ALU_BREAK: ADDR(100) CNT(3) KCACHE0(CB0:0-15) |
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| 91 | 14 z: ADD R4.z, R4.z, (0x40000000, 2.0f).x |
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| 92 | 15 x: PREDNE ____, R4.z, KC0[0].y UPDATE_EXEC_MASK UPDATE_PRED |
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| 93 | 03 TEX: ADDR(288) CNT(8) VALID_PIX |
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| 94 | 16 SAMPLE R0, R4.yz0y, t0, s0 UNNORM(XYZW) |
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| 95 | 17 SAMPLE R2, R4.yz0y, t0, s1 UNNORM(XYZW) XOFFSET(1.0) |
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| 96 | 18 SAMPLE R1, R4.xz0x, t1, s2 UNNORM(XYZW) |
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| 97 | 19 SAMPLE R3, R4.xz0x, t1, s3 UNNORM(XYZW) XOFFSET(1.0) |
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| 98 | 20 SAMPLE R5, R4.yz0y, t0, s4 UNNORM(XYZW) YOFFSET(1.0) |
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| 99 | 21 SAMPLE R6, R4.yz0y, t0, s5 UNNORM(XYZW) XOFFSET(1.0) YOFFSET(1.0) |
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| 100 | 22 SAMPLE R7, R4.xz0x, t1, s6 UNNORM(XYZW) YOFFSET(1.0) |
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| 101 | 23 SAMPLE R24, R4.xz0x, t1, s7 UNNORM(XYZW) XOFFSET(1.0) YOFFSET(1.0) |
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| 102 | 04 ALU_BREAK: ADDR(103) CNT(65) KCACHE0(CB0:0-15) |
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| 103 | 24 x: MULADD R23.x, R0.x, R1.x, R23.x |
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| 104 | y: MULADD R23.y, R0.x, R1.y, R23.y |
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| 105 | z: MULADD R23.z, R0.x, R1.z, R23.z |
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| 106 | w: MULADD R23.w, R0.x, R1.w, R23.w |
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| 107 | 25 x: MULADD R22.x, R0.y, R1.x, R22.x VEC_210 |
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| 108 | y: MULADD R22.y, R0.y, R1.y, R22.y VEC_201 |
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| 109 | z: MULADD R22.z, R0.y, R1.z, R22.z VEC_201 |
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| 110 | w: MULADD R22.w, R0.y, R1.w, R22.w VEC_201 |
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| 111 | t: MULADD R21.x, R0.z, R1.x, R21.x VEC_120 |
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| 112 | 26 x: MULADD R20.x, R0.w, R1.x, R20.x VEC_201 |
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| 113 | y: MULADD R21.y, R0.z, R1.y, R21.y VEC_210 |
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| 114 | z: MULADD R21.z, R0.z, R1.z, R21.z VEC_201 |
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| 115 | w: MULADD R21.w, R0.z, R1.w, R21.w VEC_201 |
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| 116 | t: MULADD R20.y, R0.w, R1.y, R20.y VEC_120 |
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| 117 | 27 x: MULADD R19.x, R0.x, R3.x, R19.x |
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| 118 | y: MULADD R19.y, R0.x, R3.y, R19.y |
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| 119 | z: MULADD R20.z, R0.w, R1.z, R20.z |
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| 120 | w: MULADD R20.w, R0.w, R1.w, R20.w |
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| 121 | 28 x: MULADD R18.x, R0.y, R3.x, R18.x VEC_201 |
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| 122 | y: MULADD R18.y, R0.y, R3.y, R18.y VEC_201 |
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| 123 | z: MULADD R19.z, R0.x, R3.z, R19.z VEC_210 |
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| 124 | w: MULADD R19.w, R0.x, R3.w, R19.w VEC_201 |
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| 125 | t: MULADD R18.z, R0.y, R3.z, R18.z VEC_120 |
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| 126 | 29 x: MULADD R17.x, R0.z, R3.x, R17.x VEC_201 |
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| 127 | y: MULADD R17.y, R0.z, R3.y, R17.y VEC_201 |
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| 128 | z: MULADD R17.z, R0.z, R3.z, R17.z VEC_201 |
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| 129 | w: MULADD R18.w, R0.y, R3.w, R18.w VEC_210 |
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| 130 | t: MULADD R17.w, R0.z, R3.w, R17.w VEC_120 |
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| 131 | 30 x: MULADD R16.x, R0.w, R3.x, R16.x VEC_210 |
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| 132 | y: MULADD R16.y, R0.w, R3.y, R16.y VEC_201 |
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| 133 | z: MULADD R16.z, R0.w, R3.z, R16.z VEC_201 |
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| 134 | w: MULADD R16.w, R0.w, R3.w, R16.w VEC_201 |
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| 135 | t: MULADD R10.x, R2.y, R3.x, R10.x VEC_120 |
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| 136 | 31 x: MULADD R15.x, R2.x, R1.x, R15.x |
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| 137 | y: MULADD R15.y, R2.x, R1.y, R15.y |
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| 138 | z: MULADD R15.z, R2.x, R1.z, R15.z |
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| 139 | w: MULADD R15.w, R2.x, R1.w, R15.w |
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| 140 | 32 x: MULADD R14.x, R2.y, R1.x, R14.x VEC_210 |
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| 141 | y: MULADD R14.y, R2.y, R1.y, R14.y VEC_201 |
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| 142 | z: MULADD R14.z, R2.y, R1.z, R14.z VEC_201 |
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| 143 | w: MULADD R14.w, R2.y, R1.w, R14.w VEC_201 |
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| 144 | t: MULADD R13.x, R2.z, R1.x, R13.x VEC_120 |
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| 145 | 33 x: MULADD R12.x, R2.w, R1.x, R12.x VEC_201 |
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| 146 | y: MULADD R13.y, R2.z, R1.y, R13.y VEC_210 |
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| 147 | z: MULADD R13.z, R2.z, R1.z, R13.z VEC_201 |
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| 148 | w: MULADD R13.w, R2.z, R1.w, R13.w VEC_201 |
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| 149 | t: MULADD R12.y, R2.w, R1.y, R12.y VEC_120 |
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| 150 | 34 x: MULADD R11.x, R2.x, R3.x, R11.x |
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| 151 | y: MULADD R11.y, R2.x, R3.y, R11.y |
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| 152 | z: MULADD R12.z, R2.w, R1.z, R12.z |
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| 153 | w: MULADD R12.w, R2.w, R1.w, R12.w |
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| 154 | 35 x: MULADD R8.x, R2.w, R3.x, R8.x |
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| 155 | y: MULADD R10.y, R2.y, R3.y, R10.y VEC_201 |
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| 156 | z: MULADD R11.z, R2.x, R3.z, R11.z |
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| 157 | w: MULADD R11.w, R2.x, R3.w, R11.w |
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| 158 | t: MULADD R10.z, R2.y, R3.z, R10.z |
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| 159 | 36 x: MULADD R9.x, R2.z, R3.x, R9.x VEC_201 |
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| 160 | y: MULADD R9.y, R2.z, R3.y, R9.y VEC_201 |
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| 161 | z: MULADD R9.z, R2.z, R3.z, R9.z VEC_201 |
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| 162 | w: MULADD R10.w, R2.y, R3.w, R10.w VEC_210 |
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| 163 | t: MULADD R9.w, R2.z, R3.w, R9.w VEC_120 |
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| 164 | 37 y: MULADD R8.y, R2.w, R3.y, R8.y |
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| 165 | z: MULADD R8.z, R2.w, R3.z, R8.z |
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| 166 | w: MULADD R8.w, R2.w, R3.w, R8.w |
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| 167 | 38 x: PREDNE ____, KC0[0].z, 1.0f UPDATE_EXEC_MASK UPDATE_PRED |
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| 168 | 05 ALU: ADDR(168) CNT(64) |
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| 169 | 39 x: MULADD R23.x, R5.x, R7.x, R23.x |
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| 170 | y: MULADD R23.y, R5.x, R7.y, R23.y |
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| 171 | z: MULADD R23.z, R5.x, R7.z, R23.z |
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| 172 | w: MULADD R23.w, R5.x, R7.w, R23.w |
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| 173 | 40 x: MULADD R22.x, R5.y, R7.x, R22.x VEC_210 |
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| 174 | y: MULADD R22.y, R5.y, R7.y, R22.y VEC_201 |
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| 175 | z: MULADD R22.z, R5.y, R7.z, R22.z VEC_201 |
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| 176 | w: MULADD R22.w, R5.y, R7.w, R22.w VEC_201 |
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| 177 | t: MULADD R21.x, R5.z, R7.x, R21.x VEC_120 |
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| 178 | 41 x: MULADD R20.x, R5.w, R7.x, R20.x VEC_201 |
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| 179 | y: MULADD R21.y, R5.z, R7.y, R21.y VEC_210 |
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| 180 | z: MULADD R21.z, R5.z, R7.z, R21.z VEC_201 |
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| 181 | w: MULADD R21.w, R5.z, R7.w, R21.w VEC_201 |
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| 182 | t: MULADD R20.y, R5.w, R7.y, R20.y VEC_120 |
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| 183 | 42 x: MULADD R19.x, R5.x, R24.x, R19.x |
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| 184 | y: MULADD R19.y, R5.x, R24.y, R19.y |
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| 185 | z: MULADD R20.z, R5.w, R7.z, R20.z |
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| 186 | w: MULADD R20.w, R5.w, R7.w, R20.w |
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| 187 | 43 x: MULADD R18.x, R5.y, R24.x, R18.x VEC_201 |
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| 188 | y: MULADD R18.y, R5.y, R24.y, R18.y VEC_201 |
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| 189 | z: MULADD R19.z, R5.x, R24.z, R19.z VEC_210 |
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| 190 | w: MULADD R19.w, R5.x, R24.w, R19.w VEC_201 |
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| 191 | t: MULADD R18.z, R5.y, R24.z, R18.z VEC_120 |
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| 192 | 44 x: MULADD R17.x, R5.z, R24.x, R17.x VEC_201 |
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| 193 | y: MULADD R17.y, R5.z, R24.y, R17.y VEC_201 |
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| 194 | z: MULADD R17.z, R5.z, R24.z, R17.z VEC_201 |
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| 195 | w: MULADD R18.w, R5.y, R24.w, R18.w VEC_210 |
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| 196 | t: MULADD R17.w, R5.z, R24.w, R17.w VEC_120 |
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| 197 | 45 x: MULADD R16.x, R5.w, R24.x, R16.x VEC_210 |
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| 198 | y: MULADD R16.y, R5.w, R24.y, R16.y VEC_201 |
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| 199 | z: MULADD R16.z, R5.w, R24.z, R16.z VEC_201 |
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| 200 | w: MULADD R16.w, R5.w, R24.w, R16.w VEC_201 |
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| 201 | t: MULADD R10.x, R6.y, R24.x, R10.x VEC_120 |
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| 202 | 46 x: MULADD R15.x, R6.x, R7.x, R15.x |
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| 203 | y: MULADD R15.y, R6.x, R7.y, R15.y |
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| 204 | z: MULADD R15.z, R6.x, R7.z, R15.z |
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| 205 | w: MULADD R15.w, R6.x, R7.w, R15.w |
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| 206 | 47 x: MULADD R14.x, R6.y, R7.x, R14.x VEC_210 |
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| 207 | y: MULADD R14.y, R6.y, R7.y, R14.y VEC_201 |
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| 208 | z: MULADD R14.z, R6.y, R7.z, R14.z VEC_201 |
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| 209 | w: MULADD R14.w, R6.y, R7.w, R14.w VEC_201 |
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| 210 | t: MULADD R13.x, R6.z, R7.x, R13.x VEC_120 |
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| 211 | 48 x: MULADD R12.x, R6.w, R7.x, R12.x VEC_201 |
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| 212 | y: MULADD R13.y, R6.z, R7.y, R13.y VEC_210 |
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| 213 | z: MULADD R13.z, R6.z, R7.z, R13.z VEC_201 |
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| 214 | w: MULADD R13.w, R6.z, R7.w, R13.w VEC_201 |
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| 215 | t: MULADD R12.y, R6.w, R7.y, R12.y VEC_120 |
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| 216 | 49 x: MULADD R11.x, R6.x, R24.x, R11.x |
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| 217 | y: MULADD R11.y, R6.x, R24.y, R11.y |
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| 218 | z: MULADD R12.z, R6.w, R7.z, R12.z |
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| 219 | w: MULADD R12.w, R6.w, R7.w, R12.w |
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| 220 | 50 x: MULADD R8.x, R6.w, R24.x, R8.x |
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| 221 | y: MULADD R10.y, R6.y, R24.y, R10.y VEC_201 |
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| 222 | z: MULADD R11.z, R6.x, R24.z, R11.z |
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| 223 | w: MULADD R11.w, R6.x, R24.w, R11.w |
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| 224 | t: MULADD R10.z, R6.y, R24.z, R10.z |
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| 225 | 51 x: MULADD R9.x, R6.z, R24.x, R9.x VEC_201 |
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| 226 | y: MULADD R9.y, R6.z, R24.y, R9.y VEC_201 |
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| 227 | z: MULADD R9.z, R6.z, R24.z, R9.z VEC_201 |
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| 228 | w: MULADD R10.w, R6.y, R24.w, R10.w VEC_210 |
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| 229 | t: MULADD R9.w, R6.z, R24.w, R9.w VEC_120 |
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| 230 | 52 y: MULADD R8.y, R6.w, R24.y, R8.y |
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| 231 | z: MULADD R8.z, R6.w, R24.z, R8.z |
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| 232 | w: MULADD R8.w, R6.w, R24.w, R8.w |
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| 233 | 06 ENDLOOP i0 PASS_JUMP_ADDR(2) |
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| 234 | 07 ALU: ADDR(232) CNT(21) KCACHE0(CB0:0-15) |
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| 235 | 53 y: MOV*4 R0.y, R4.y |
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| 236 | z: NOP ____ |
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| 237 | t: F_TO_I T0.z, KC0[0].x |
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| 238 | 54 x: LSHL R4.x, PS53, 1 |
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| 239 | y: MULADD R123.y, PV53.y, KC0[0].x, R4.x |
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| 240 | 55 x: MOV R3.x, 0.0f |
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| 241 | y: MOV R3.y, 0.0f |
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| 242 | z: MOV R3.z, 0.0f |
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| 243 | w: MOV R3.w, 0.0f |
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| 244 | t: F_TO_I ____, PV54.y |
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| 245 | 56 x: LSHL R0.x, PS55, (0x00000002, 2.802596929e-45f).x |
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| 246 | y: ADD_INT ____, PS55, 1 |
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| 247 | z: ADD_INT R1.z, PS55, R4.x |
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| 248 | w: ADD_INT ____, PS55, T0.z |
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| 249 | 57 x: LSHL R1.x, PV56.y, (0x00000002, 2.802596929e-45f).x |
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| 250 | y: ADD_INT R0.y, PV56.y, R4.x |
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| 251 | z: ADD_INT R0.z, PV56.y, T0.z |
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| 252 | w: ADD_INT R0.w, PV56.w, R4.x |
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| 253 | t: LSHL R2.x, PV56.w, (0x00000002, 2.802596929e-45f).x |
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| 254 | 08 MEM_EXPORT_WRITE_IND: DWORD_PTR[0+R0.x], R23, ELEM_SIZE(3) VPM |
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| 255 | 09 MEM_EXPORT_WRITE_IND: DWORD_PTR[0+R1.x], R19, ELEM_SIZE(3) VPM |
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| 256 | 10 MEM_EXPORT_WRITE_IND: DWORD_PTR[0+R2.x], R22, ELEM_SIZE(3) VPM |
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| 257 | 11 EXP_DONE: PIX0, R3 |
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| 258 | 12 ALU: ADDR(253) CNT(12) |
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| 259 | 58 x: LSHL R2.x, R0.z, (0x00000002, 2.802596929e-45f).x |
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| 260 | y: ADD_INT R1.y, R4.x, R0.y |
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| 261 | z: ADD_INT R0.z, R4.x, R1.z |
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| 262 | w: ADD_INT R1.w, R0.z, R4.x |
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| 263 | t: LSHL R1.x, R1.z, (0x00000002, 2.802596929e-45f).x |
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| 264 | 59 x: LSHL R0.x, R0.y, (0x00000002, 2.802596929e-45f).x |
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| 265 | y: ADD_INT R0.y, R4.x, PV58.z |
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| 266 | z: ADD_INT R1.z, R4.x, PV58.w |
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| 267 | w: ADD_INT R0.w, R4.x, R0.w |
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| 268 | t: LSHL R3.x, R0.w, (0x00000002, 2.802596929e-45f).x |
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| 269 | 13 MEM_EXPORT_WRITE_IND: DWORD_PTR[0+R2.x], R18, ELEM_SIZE(3) VPM |
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| 270 | 14 MEM_EXPORT_WRITE_IND: DWORD_PTR[0+R1.x], R21, ELEM_SIZE(3) VPM |
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| 271 | 15 MEM_EXPORT_WRITE_IND: DWORD_PTR[0+R0.x], R17, ELEM_SIZE(3) VPM |
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| 272 | 16 MEM_EXPORT_WRITE_IND: DWORD_PTR[0+R3.x], R20, ELEM_SIZE(3) VPM |
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| 273 | 17 ALU: ADDR(265) CNT(9) |
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| 274 | 60 x: LSHL R4.x, R1.w, (0x00000002, 2.802596929e-45f).x |
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| 275 | y: ADD_INT R2.y, R4.x, R1.z |
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| 276 | z: ADD_INT R0.z, R4.x, R0.w |
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| 277 | w: ADD_INT R1.w, R4.x, R1.y |
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| 278 | t: LSHL R3.x, R0.z, (0x00000002, 2.802596929e-45f).x |
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| 279 | 61 x: LSHL R0.x, R1.y, (0x00000002, 2.802596929e-45f).x |
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| 280 | t: LSHL R1.x, R0.w, (0x00000002, 2.802596929e-45f).x |
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| 281 | 18 MEM_EXPORT_WRITE_IND: DWORD_PTR[0+R4.x], R16, ELEM_SIZE(3) VPM |
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| 282 | 19 MEM_EXPORT_WRITE_IND: DWORD_PTR[0+R3.x], R15, ELEM_SIZE(3) VPM |
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| 283 | 20 MEM_EXPORT_WRITE_IND: DWORD_PTR[0+R0.x], R11, ELEM_SIZE(3) VPM |
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| 284 | 21 MEM_EXPORT_WRITE_IND: DWORD_PTR[0+R1.x], R14, ELEM_SIZE(3) VPM |
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| 285 | 22 ALU: ADDR(274) CNT(6) |
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| 286 | 62 x: LSHL R1.x, R1.z, (0x00000002, 2.802596929e-45f).x |
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| 287 | t: LSHL R0.x, R0.y, (0x00000002, 2.802596929e-45f).x |
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| 288 | 63 x: LSHL R3.x, R1.w, (0x00000002, 2.802596929e-45f).x |
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| 289 | t: LSHL R4.x, R0.z, (0x00000002, 2.802596929e-45f).x |
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| 290 | 23 MEM_EXPORT_WRITE_IND: DWORD_PTR[0+R1.x], R10, ELEM_SIZE(3) VPM |
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| 291 | 24 MEM_EXPORT_WRITE_IND: DWORD_PTR[0+R0.x], R13, ELEM_SIZE(3) VPM |
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| 292 | 25 MEM_EXPORT_WRITE_IND: DWORD_PTR[0+R3.x], R9, ELEM_SIZE(3) VPM |
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| 293 | 26 MEM_EXPORT_WRITE_IND: DWORD_PTR[0+R4.x], R12, ELEM_SIZE(3) VPM |
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| 294 | 27 ALU: ADDR(280) CNT(2) |
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| 295 | 64 x: LSHL R4.x, R2.y, (0x00000002, 2.802596929e-45f).x |
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| 296 | 28 MEM_EXPORT_WRITE_IND: DWORD_PTR[0+R4.x], R8, ELEM_SIZE(3) VPM |
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| 297 | END_OF_PROGRAM |
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| 298 | |
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| 299 | ; ----------------- PS Data ------------------------ |
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| 300 | ; Input Semantic Mappings |
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| 301 | IN PARAM0 = position0 V0.xxxx DefaultVal={0,0,0,0} |
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| 302 | |
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| 303 | NumTexStages = 0 |
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| 304 | |
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| 305 | TexCubeMaskBits = 0x00000000 |
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| 306 | |
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| 307 | GprPoolSize = 0 |
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| 308 | CodeLen = 2432;Bytes |
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| 309 | PGM_END_CF = 0; words(64 bit) |
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| 310 | PGM_END_ALU = 0; words(64 bit) |
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| 311 | PGM_END_FETCH = 0; words(64 bit) |
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| 312 | MaxScratchRegsNeeded = 0 |
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| 313 | ;AluPacking = 0.0 |
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| 314 | ;AluClauses = 0 |
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| 315 | ;PowerThrottleRate = 0.0 |
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| 316 | ; texResourceUsage[0] = 0x00000000 |
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| 317 | ; texResourceUsage[1] = 0x00000000 |
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| 318 | ; texResourceUsage[2] = 0x00000000 |
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| 319 | ; texResourceUsage[3] = 0x00000000 |
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| 320 | ; fetch4ResourceUsage[0] = 0x00000000 |
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| 321 | ; fetch4ResourceUsage[1] = 0x00000000 |
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| 322 | ; fetch4ResourceUsage[2] = 0x00000000 |
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| 323 | ; fetch4ResourceUsage[3] = 0x00000000 |
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| 324 | ; texSamplerUsage = 0x00000000 |
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| 325 | ; constBufUsage = 0x00000000 |
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| 326 | ResourcesAffectAlphaOutput[0] = 0x00000000 |
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| 327 | ResourcesAffectAlphaOutput[1] = 0x00000000 |
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| 328 | ResourcesAffectAlphaOutput[2] = 0x00000000 |
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| 329 | ResourcesAffectAlphaOutput[3] = 0x00000000 |
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| 330 | |
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| 331 | ;SQ_PGM_RESOURCES = 0x70000119 |
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| 332 | SQ_PGM_RESOURCES:NUM_GPRS = 25 |
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| 333 | SQ_PGM_RESOURCES:STACK_SIZE = 1 |
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| 334 | SQ_PGM_RESOURCES:PRIME_CACHE_ENABLE = 1 |
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| 335 | ;SQ_PGM_RESOURCES_2 = 0x000000C0 |
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| 336 | SQ_LDS_ALLOC_PS:SIZE = 0x00000000 |
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| 337 | ; SPI_PS_IN_CONTROL_0 = 0x00000100 |
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| 338 | SPI0:NUM_INTERP = 0 |
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| 339 | SPI0:POSITION_ENA = 1 |
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| 340 | SPI0:POSITION_CENTROID = 0 |
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| 341 | SPI0:POSITION_ADDR = 0 |
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| 342 | SPI0:PARAM_GEN = 0 |
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| 343 | SPI0:PERSP_GRADIENT_ENA = 0 |
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| 344 | SPI0:LINEAR_GRADIENT_ENA = 0 |
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| 345 | SPI0:POSITION_SAMPLE = 0 |
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| 346 | ; SPI_PS_IN_CONTROL_1 = 0x00000000 |
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| 347 | SPI1:GEN_INDEX_PIX = 0 |
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| 348 | SPI1:FIXED_PT_POSITION_ENA = 0 |
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| 349 | SPI1:FIXED_PT_POSITION_ADDR = 0 |
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| 350 | SPI1:FRONT_FACE_ENA = 0 |
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| 351 | SPI1:FRONT_FACE_ADDR = 0 |
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| 352 | SPI1:FOG_ADDR = 0 |
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| 353 | ; SPI_PS_IN_CONTROL_2 = 0x00000000 |
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| 354 | ; SPI_BARYC_CNTL = 0x00000001 |
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| 355 | SPI_BARYC_CNTL:PERSP_CENTER_ENA = 1 |
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| 356 | SPI_BARYC_CNTL:PERSP_CENTROID_ENA = 0 |
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| 357 | SPI_BARYC_CNTL:PERSP_SAMPLE_ENA = 0 |
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| 358 | SPI_BARYC_CNTL:PERSP_PULL_MODEL_ENA = 0 |
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| 359 | SPI_BARYC_CNTL:LINEAR_CENTER_ENA = 0 |
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| 360 | SPI_BARYC_CNTL:LINEAR_CENTROID_ENA = 0 |
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| 361 | SPI_BARYC_CNTL:LINEAR_SAMPLE_ENA = 0 |
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| 362 | ; SPI_INPUT_Z |
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| 363 | SPI:PROVIDE_Z_TO_SPI = 0 |
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| 364 | ; CB_SHADER_MASK = 0x0000000F |
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| 365 | CB:OUTPUT0_ENABLE = 15 |
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| 366 | ; DB_SHADER_CONTROL = 0x00004600 |
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| 367 | DB:Z_EXPORT_ENABLE = 0 |
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| 368 | DB:STENCIL_REF_EXPORT_ENABLE = 0 |
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| 369 | DB:MASK_EXPORT_ENABLE = 0 |
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| 370 | DB:ALPHA_TO_MASK_DISABLE = 0 |
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| 371 | DB:Z_ORDER = 0 |
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| 372 | DB:KILL_ENABLE = 0 |
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| 373 | DB:DB_SOURCE_FORMAT = 2 |
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| 374 | DB:CONSERVATIVE_Z_EXPORT = 0 |
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| 375 | DB:DEPTH_BEFORE_SHADER = 0 |
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| 376 | DB:EXEC_ON_HIER_FAIL = 1 |
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| 377 | ; SQ_PGM_EXPORTS_PS |
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| 378 | SQ_PGM_EXPORTS_PS:PS_EXPORT_MODE = 0x00000002 ; (1 color) |
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| 379 | |
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