verilog MIPSmodule.v testfixture_sample.v 
Tool:	VERILOG-XL	05.60.001-p   Jul 19, 2011  10:42:31

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Compiling source file "MIPSmodule.v"
Compiling included source file "../rtl/opdef_pipe.v"
Continuing compilation of source file "MIPSmodule.v"
Compiling included source file "../rtl/mipspipe.v"
Continuing compilation of source file "MIPSmodule.v"
Compiling included source file "../rtl/mipsalu.v"
Continuing compilation of source file "MIPSmodule.v"
Compiling included source file "../rtl/regfile.v"
Continuing compilation of source file "MIPSmodule.v"
Compiling included source file "../rtl/alucontrol.v"
Continuing compilation of source file "MIPSmodule.v"
Compiling included source file "../rtl/instdec_pipe.v"
Continuing compilation of source file "MIPSmodule.v"
Compiling included source file "../rtl/basicmodules.v"
Continuing compilation of source file "MIPSmodule.v"
Compiling included source file "../rtl/ext.v"
Continuing compilation of source file "MIPSmodule.v"
Compiling included source file "../rtl/memoryif.v"
Continuing compilation of source file "MIPSmodule.v"
Compiling included source file "../rtl/hazard.v"
Continuing compilation of source file "MIPSmodule.v"
Compiling included source file "../rtl/forward.v"
Continuing compilation of source file "MIPSmodule.v"
Compiling source file "testfixture_sample.v"
Highest level modules:
mux8
mipspipe_sample

RESULT:
00000077
L70 "testfixture_sample.v": $finish at simulation time 3110
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.0 secs to compile + 0.3 secs to link + 0.1 secs in simulation
End of Tool:	VERILOG-XL	05.60.001-p   Jul 19, 2011  10:42:33
simvision mipspipe_sample.vcd &
txe: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
