Changes between Version 3 and Version 4 of Ex06課題2015

Timestamp:

May 18, 2015 10:26:24 AM (11 years ago)

Author:

nakasato

Comment:

--

Ex06課題2015

@@ -83 +83 @@
 = 課題2 メモリの利用方法 =
 以下のテストベンチファイルでは、レジスタファイルとメモリとALUをインスタンス化し、テストするためのテンプレートである。
-
-http://galaxy.u-aizu.ac.jp/comparch2014/test_mem.v
+{{{
+`timescale 1ns/1ps
+`include "Registers.v"
+`include "Memory.v"
+`include "ALU.v"
+
+module  MemTest;
+   // for Memory
+   reg [31:0] address;
+   reg [31:0] write_data;
+   reg        write_enable, read_enable;
+   reg        ck;
+   wire [31:0] read_data;
+
+   // for Registers
+   reg [4:0]  read_adr1_reg, read_adr2_reg, write_adr_reg;
+   reg [31:0] write_data_reg;
+   reg        write_enable_reg;
+   reg        clear_reg;
+   wire [31:0] read_data1_reg, read_data2_reg;
+
+   // for ALU
+   reg [31:0]  A, B;
+   reg [3:0]   ALUop;
+   wire        Zero;
+   wire [31:0] Result;
+      
+   Memory    mem(address, write_data, read_data, write_enable, read_enable, ck);
+
+   Registers regs(read_adr1_reg, read_adr2_reg, write_data_reg, write_enable_reg, write_adr_reg,
+                  ck, clear_reg,
+                  read_data1_reg, read_data2_reg);
+
+   ALU       alu(A, B, ALUop, Result, Zero);
+      
+   initial
+     begin
+        $dumpfile("MemTest.vcd");
+        $dumpvars(0, MemTest);
+        
+        // data segment
+        Mem.cell['h00005000] = 32'h0000000a;
+        Mem.cell['h00005004] = 32'h0000000b;
+        Mem.cell['h00005008] = 32'h00000000;
+        Mem.cell['h00005010] = 32'h00000000;
+        Mem.cell['h00005014] = 32'h00000000;
+        Mem.cell['h00005018] = 32'h00000000;
+
+        #0
+        ck = 1'b1;
+        clear_reg = 1'b1;
+        
+        read_enable = 1'b0;
+        address = 32'h00000000;
+        write_enable_reg = 1'b0;        
+        write_adr_reg    = 5'b00000;    
+        write_data_reg   = 32'h00000000;
+        
+        #110
+        clear_reg = 1'b0;
+
+        #190 // read memory at 0x5000
+        read_enable = 1'b1;
+        address = 32'h00005000;
+
+        #100 // write data to $v0 and read memory at 0x5004
+        write_enable_reg = 1'b1;
+        write_adr_reg    = 5'b00010;
+        write_data_reg   = read_data;
+
+        #100
+        read_enable = 1'b0;
+        write_enable_reg = 1'b0;
+
+        #100
+        read_adr1_reg = 5'b00010;
+
+        #100
+        $display("$v0 = %x",read_data1_reg);      
+
+        #2000
+        
+        $finish;
+     end // initial begin
+   
+   always #50 ck = ~ck;
+endmodule
+}}}
 
 実行結果は以下のようになるはずである。