Ex08課題2015: CUbench.v

File CUbench.v, 6.6 KB (added by nakasato, 11 years ago)
Line 
1`timescale 1ns/1ps
2`include "ControlUnit.v"
3
4
5module CUbench;
6
7   reg ck;
8   reg clr;
9   reg [5:0] op;
10
11   wire      pcwritecond;
12   wire      pcwrite;
13   wire      iord;
14   wire      memread;
15   wire      memwrite;
16   wire      memtoreg;
17   wire      irwrite;
18   wire [1:0] pcsource;
19   wire [1:0] aluop;
20   wire [2:0] alusrcb;
21   wire       alusrca;
22   wire       regwrite;
23   wire       regdst;
24
25   ControlUnit cu(.PCWriteCond(pcwritecond), .PCWrite(pcwrite), .IorD(iord), .MemRead(memread), .MemWrite(memwrite), .MemtoReg(memtoreg), .IRWrite(irwrite), .PCSource(pcsource), .ALUOp(aluop), .ALUSrcB(alusrcb), .ALUSrcA(alusrca), .RegWrite(regwrite), .RegDST(regdst), .Op(op), .CK(ck), .CLR(clr));
26
27
28   initial
29     begin
30
31        $dumpfile("CUbench.vcd");
32        $dumpvars(0, cu);
33
34        // initialize
35        #0
36        ck = 1'b1;
37        clr = 1'b1;
38        op = 0;
39 
40        #125
41        clr = 1'b0;
42
43        // operation = LW
44        op = 35; 
45        #75
46        $display("\noperation = LW");
47        $display("state=%d: MemRead=%b,ALUSrcA=%b,IorD=%b,IRWrite=%b,ALUSrcB=%b,ALUOp=%b,PCWrite=%b,PCSource=%b",cu.state,cu.MemRead,cu.ALUSrcA,cu.IorD,cu.IRWrite,cu.ALUSrcB,cu.ALUOp,cu.PCWrite,cu.PCSource);
48        #100
49          $display("state=%d: ALUSrcA=%b,ALUSrcB=%b,ALUOp=%b",cu.state,cu.ALUSrcA,cu.ALUSrcB,cu.ALUOp);
50        #100
51          $display("state=%d: ALUSrcA=%b,ALUSrcB=%b,ALUOp=%b",cu.state,cu.ALUSrcA,cu.ALUSrcB,cu.ALUOp);
52        #100
53          $display("state=%d: MemRead=%b,IorD=%b",cu.state,cu.MemRead,cu.IorD);
54        #100
55          $display("state=%d: RegDst=%b,RegWrite=%b,MemtoReg=%b\n",cu.state,cu.RegDST,cu.RegWrite,cu.MemtoReg);
56
57        // reset 
58        #75
59        clr = 1'b1;
60        #50
61        clr = 1'b0;
62
63        // operation = SW
64        op = 43;
65        #75
66        $display("\noperation = SW");
67        $display("state=%d: MemRead=%b,ALUSrcA=%b,IorD=%b,IRWrite=%b,ALUSrcB=%b,ALUOp=%b,PCWrite=%b,PCSource=%b",cu.state,cu.MemRead,cu.ALUSrcA,cu.IorD,cu.IRWrite,cu.ALUSrcB,cu.ALUOp,cu.PCWrite,cu.PCSource);
68        #100
69          $display("state=%d: ALUSrcA=%b,ALUSrcB=%b,ALUOp=%b",cu.state,cu.ALUSrcA,cu.ALUSrcB,cu.ALUOp);
70        #100
71          $display("state=%d: ALUSrcA=%b,ALUSrcB=%b,ALUOp=%b",cu.state,cu.ALUSrcA,cu.ALUSrcB,cu.ALUOp);
72        #100
73          $display("state=%d: MemWrite=%b,IorD=%b\n",cu.state,cu.MemWrite,cu.IorD);
74
75        // reset 
76        clr = 1'b0;
77        #75
78        clr = 1'b1;
79        #50
80        clr = 1'b0;
81
82        // operation = RTYPE(register type)
83        op = 0; 
84        #75
85        $display("\noperation = RTYPE");
86        $display("state=%d: MemRead=%b,ALUSrcA=%b,IorD=%b,IRWrite=%b,ALUSrcB=%b,ALUOp=%b,PCWrite=%b,PCSource=%b",cu.state,cu.MemRead,cu.ALUSrcA,cu.IorD,cu.IRWrite,cu.ALUSrcB,cu.ALUOp,cu.PCWrite,cu.PCSource);
87        #100
88          $display("state=%d: ALUSrcA=%b,ALUSrcB=%b,ALUOp=%b",cu.state,cu.ALUSrcA,cu.ALUSrcB,cu.ALUOp);
89        #100
90          $display("state=%d: ALUSrcA=%b,ALUSrcB=%b,ALUOp=%b",cu.state,cu.ALUSrcA,cu.ALUSrcB,cu.ALUOp);
91        #100
92          $display("state=%d: RegDst=%b,RegWrite=%b,MemtoReg=%b\n",cu.state,cu.RegDST,cu.RegWrite,cu.MemtoReg);
93
94        // reset 
95        clr = 1'b0;
96        #75
97        clr = 1'b1;
98        #50
99        clr = 1'b0;
100
101        // operation = BEQ
102        op = 4; 
103        #75
104        $display("\noperation = BEQ");
105        $display("state=%d: MemRead=%b,ALUSrcA=%b,IorD=%b,IRWrite=%b,ALUSrcB=%b,ALUOp=%b,PCWrite=%b,PCSource=%b",cu.state,cu.MemRead,cu.ALUSrcA,cu.IorD,cu.IRWrite,cu.ALUSrcB,cu.ALUOp,cu.PCWrite,cu.PCSource);
106        #100
107          $display("state=%d: ALUSrcA=%b,ALUSrcB=%b,ALUOp=%b",cu.state,cu.ALUSrcA,cu.ALUSrcB,cu.ALUOp);
108        #100
109          $display("state=%d: ALUSrcA=%b,ALUSrcB=%b,ALUOp=%b,PCWriteCond=%b,PCSource=%b\n",cu.state,cu.ALUSrcA,cu.ALUSrcB,cu.ALUOp,cu.PCWriteCond,cu.PCSource);
110
111        // reset 
112        clr = 1'b0;
113        #75
114        clr = 1'b1;
115        #50
116        clr = 1'b0;
117
118        // operation = JMP
119        op = 2; 
120        #75
121        $display("\noperation = JMP");
122        $display("state=%d: MemRead=%b,ALUSrcA=%b,IorD=%b,IRWrite=%b,ALUSrcB=%b,ALUOp=%b,PCWrite=%b,PCSource=%b",cu.state,cu.MemRead,cu.ALUSrcA,cu.IorD,cu.IRWrite,cu.ALUSrcB,cu.ALUOp,cu.PCWrite,cu.PCSource);
123        #100
124          $display("state=%d: ALUSrcA=%b,ALUSrcB=%b,ALUOp=%b",cu.state,cu.ALUSrcA,cu.ALUSrcB,cu.ALUOp);
125        #100
126          $display("state=%d: PCWrite=%b,PCSource=%b\n",cu.state,cu.PCWrite,cu.PCSource);
127
128        // reset 
129        clr = 1'b0;
130        #75
131        clr = 1'b1;
132        #50
133        clr = 1'b0;
134
135        // operation = ADDI
136        op = 8; 
137        #75
138        $display("\noperation = ADDI");
139        $display("state=%d: MemRead=%b,ALUSrcA=%b,IorD=%b,IRWrite=%b,ALUSrcB=%b,ALUOp=%b,PCWrite=%b,PCSource=%b",cu.state,cu.MemRead,cu.ALUSrcA,cu.IorD,cu.IRWrite,cu.ALUSrcB,cu.ALUOp,cu.PCWrite,cu.PCSource);
140        #100
141          $display("state=%d: ALUSrcA=%b,ALUSrcB=%b,ALUOp=%b",cu.state,cu.ALUSrcA,cu.ALUSrcB,cu.ALUOp);
142        #100
143          $display("state=%d: ALUSrcA=%b,ALUSrcB=%b,ALUOp=%b",cu.state,cu.ALUSrcA,cu.ALUSrcB,cu.ALUOp);
144        #100
145          $display("state=%d: RegDst=%b,RegWrite=%b,MemtoReg=%b\n",cu.state,cu.RegDST,cu.RegWrite,cu.MemtoReg);
146
147        // reset 
148        clr = 1'b0;
149        #75
150        clr = 1'b1;
151        #50
152        clr = 1'b0;
153
154        // operation = SLTI
155        op = 10; 
156        #75
157        $display("\noperation = SLTI");
158        $display("state=%d: MemRead=%b,ALUSrcA=%b,IorD=%b,IRWrite=%b,ALUSrcB=%b,ALUOp=%b,PCWrite=%b,PCSource=%b",cu.state,cu.MemRead,cu.ALUSrcA,cu.IorD,cu.IRWrite,cu.ALUSrcB,cu.ALUOp,cu.PCWrite,cu.PCSource);
159        #100
160          $display("state=%d: ALUSrcA=%b,ALUSrcB=%b,ALUOp=%b",cu.state,cu.ALUSrcA,cu.ALUSrcB,cu.ALUOp);
161        #100
162          $display("state=%d: ALUSrcA=%b,ALUSrcB=%b,ALUOp=%b",cu.state,cu.ALUSrcA,cu.ALUSrcB,cu.ALUOp);
163        #100
164          $display("state=%d: RegDst=%b,RegWrite=%b,MemtoReg=%b\n",cu.state,cu.RegDST,cu.RegWrite,cu.MemtoReg);
165
166        // reset 
167        clr = 1'b0;
168        #75
169        clr = 1'b1;
170        #50
171        clr = 1'b0;
172
173
174        // operation = ANDI
175        op = 12; 
176        #75
177        $display("\noperation = ANDI");
178        $display("state=%d: MemRead=%b,ALUSrcA=%b,IorD=%b,IRWrite=%b,ALUSrcB=%b,ALUOp=%b,PCWrite=%b,PCSource=%b",cu.state,cu.MemRead,cu.ALUSrcA,cu.IorD,cu.IRWrite,cu.ALUSrcB,cu.ALUOp,cu.PCWrite,cu.PCSource);
179        #100
180          $display("state=%d: ALUSrcA=%b,ALUSrcB=%b,ALUOp=%b",cu.state,cu.ALUSrcA,cu.ALUSrcB,cu.ALUOp);
181        #100
182          $display("state=%d: ALUSrcA=%b,ALUSrcB=%b,ALUOp=%b",cu.state,cu.ALUSrcA,cu.ALUSrcB,cu.ALUOp);
183        #100
184          $display("state=%d: RegDst=%b,RegWrite=%b,MemtoReg=%b\n",cu.state,cu.RegDST,cu.RegWrite,cu.MemtoReg);
185
186
187        // reset 
188        clr = 1'b0;
189        #75
190        clr = 1'b1;
191        #50
192        clr = 1'b0;
193
194
195        // operation = ORI
196        op = 13; 
197        #75
198        $display("\noperation = ORI");
199        $display("state=%d: MemRead=%b,ALUSrcA=%b,IorD=%b,IRWrite=%b,ALUSrcB=%b,ALUOp=%b,PCWrite=%b,PCSource=%b",cu.state,cu.MemRead,cu.ALUSrcA,cu.IorD,cu.IRWrite,cu.ALUSrcB,cu.ALUOp,cu.PCWrite,cu.PCSource);
200        #100
201          $display("state=%d: ALUSrcA=%b,ALUSrcB=%b,ALUOp=%b",cu.state,cu.ALUSrcA,cu.ALUSrcB,cu.ALUOp);
202        #100
203          $display("state=%d: ALUSrcA=%b,ALUSrcB=%b,ALUOp=%b",cu.state,cu.ALUSrcA,cu.ALUSrcB,cu.ALUOp);
204        #100
205          $display("state=%d: RegDst=%b,RegWrite=%b,MemtoReg=%b\n",cu.state,cu.RegDST,cu.RegWrite,cu.MemtoReg);
206
207        #200
208
209        $finish;
210     end
211
212   always #50 ck = ~ck;
213
214endmodule